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3373 gcc >= 4.5 concerns about offsetof()
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--- old/usr/src/uts/common/sys/ecppvar.h
+++ new/usr/src/uts/common/sys/ecppvar.h
1 1 /*
2 2 * CDDL HEADER START
3 3 *
4 4 * The contents of this file are subject to the terms of the
5 5 * Common Development and Distribution License, Version 1.0 only
6 6 * (the "License"). You may not use this file except in compliance
7 7 * with the License.
8 8 *
9 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 10 * or http://www.opensolaris.org/os/licensing.
11 11 * See the License for the specific language governing permissions
12 12 * and limitations under the License.
13 13 *
14 14 * When distributing Covered Code, include this CDDL HEADER in each
15 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 16 * If applicable, add the following below this CDDL HEADER, with the
17 17 * fields enclosed by brackets "[]" replaced with your own identifying
18 18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 19 *
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20 20 * CDDL HEADER END
21 21 */
22 22 /*
23 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
24 24 * Use is subject to license terms.
25 25 */
26 26
27 27 #ifndef _SYS_ECPPVAR_H
28 28 #define _SYS_ECPPVAR_H
29 29
30 -#pragma ident "%Z%%M% %I% %E% SMI"
31 -
32 30 #include <sys/note.h>
33 31
34 32 #ifdef __cplusplus
35 33 extern "C" {
36 34 #endif
37 35
38 36 struct ecppunit;
39 37
40 38 /*
41 39 * Hardware-abstraction structure
42 40 */
43 41 struct ecpp_hw {
44 42 int (*map_regs)(struct ecppunit *); /* map registers */
45 43 void (*unmap_regs)(struct ecppunit *); /* unmap registers */
46 44 int (*config_chip)(struct ecppunit *); /* configure SuperIO */
47 45 void (*config_mode)(struct ecppunit *); /* config new mode */
48 46 void (*mask_intr)(struct ecppunit *); /* mask interrupts */
49 47 void (*unmask_intr)(struct ecppunit *); /* unmask interrupts */
50 48 int (*dma_start)(struct ecppunit *); /* start DMA transfer */
51 49 int (*dma_stop)(struct ecppunit *, size_t *); /* stop DMA xfer */
52 50 size_t (*dma_getcnt)(struct ecppunit *); /* get DMA counter */
53 51 ddi_dma_attr_t *attr; /* DMA attributes */
54 52 };
55 53
56 54 #define ECPP_MAP_REGS(pp) (pp)->hw->map_regs(pp)
57 55 #define ECPP_UNMAP_REGS(pp) (pp)->hw->unmap_regs(pp)
58 56 #define ECPP_CONFIG_CHIP(pp) (pp)->hw->config_chip(pp)
59 57 #define ECPP_CONFIG_MODE(pp) (pp)->hw->config_mode(pp)
60 58 #define ECPP_MASK_INTR(pp) (pp)->hw->mask_intr(pp)
61 59 #define ECPP_UNMASK_INTR(pp) (pp)->hw->unmask_intr(pp)
62 60 #define ECPP_DMA_START(pp) (pp)->hw->dma_start(pp)
63 61 #define ECPP_DMA_STOP(pp, cnt) (pp)->hw->dma_stop(pp, cnt)
64 62 #define ECPP_DMA_GETCNT(pp) (pp)->hw->dma_getcnt(pp)
65 63
66 64 /* NSC 87332/97317 and EBus DMAC */
67 65 struct ecpp_ebus {
68 66 struct config_reg *c_reg; /* configuration registers */
69 67 ddi_acc_handle_t c_handle; /* handle for conf regs */
70 68 struct cheerio_dma_reg *dmac; /* ebus dmac registers */
71 69 ddi_acc_handle_t d_handle; /* handle for dmac registers */
72 70 struct config2_reg *c2_reg; /* 97317 2nd level conf regs */
73 71 ddi_acc_handle_t c2_handle; /* handle for c2_reg */
74 72 };
75 73
76 74 /* Southbridge SuperIO and 8237 DMAC */
77 75 struct ecpp_m1553 {
78 76 struct isaspace *isa_space; /* all of isa space */
79 77 ddi_acc_handle_t d_handle; /* handle for isa space */
80 78 uint8_t chn; /* 8237 dma channel */
81 79 int isadma_entered; /* Southbridge DMA workaround */
82 80 };
83 81
84 82 #if defined(__x86)
85 83 struct ecpp_x86 {
86 84 uint8_t chn;
87 85 };
88 86 #endif
89 87
90 88 /*
91 89 * Hardware binding structure
92 90 */
93 91 struct ecpp_hw_bind {
94 92 char *name; /* binding name */
95 93 struct ecpp_hw *hw; /* hw description */
96 94 char *info; /* info string */
97 95 };
98 96
99 97 /*
100 98 * ecpp soft state structure
101 99 */
102 100 struct ecppunit {
103 101 kmutex_t umutex; /* lock for this structure */
104 102 int instance; /* instance number */
105 103 dev_info_t *dip; /* device information */
106 104 ddi_iblock_cookie_t ecpp_trap_cookie; /* interrupt cookie */
107 105 boolean_t e_busy; /* ecpp busy flag */
108 106 kcondvar_t pport_cv; /* cv to signal idle state */
109 107 /*
110 108 * common SuperIO registers
111 109 */
112 110 struct info_reg *i_reg; /* info registers */
113 111 struct fifo_reg *f_reg; /* fifo register */
114 112 ddi_acc_handle_t i_handle;
115 113 ddi_acc_handle_t f_handle;
116 114 /*
117 115 * DMA support
118 116 */
119 117 ddi_dma_handle_t dma_handle; /* DMA handle */
120 118 ddi_dma_cookie_t dma_cookie; /* current cookie */
121 119 uint_t dma_cookie_count; /* # of cookies */
122 120 uint_t dma_nwin; /* # of DMA windows */
123 121 uint_t dma_curwin; /* current window number */
124 122 uint_t dma_dir; /* transfer direction */
125 123 /*
126 124 * hardware-dependent stuff
127 125 */
128 126 struct ecpp_hw *hw; /* operations/attributes */
129 127 union { /* hw-dependent data */
130 128 struct ecpp_ebus ebus;
131 129 struct ecpp_m1553 m1553;
132 130 #if defined(__x86)
133 131 struct ecpp_x86 x86;
134 132 #endif
135 133 } uh;
136 134 /*
137 135 * DDI/STREAMS stuff
138 136 */
139 137 boolean_t oflag; /* instance open flag */
140 138 queue_t *readq; /* pointer to readq */
141 139 queue_t *writeq; /* pointer to writeq */
142 140 mblk_t *msg; /* current message block */
143 141 boolean_t suspended; /* driver suspended status */
144 142 /*
145 143 * Modes of operation
146 144 */
147 145 int current_mode; /* 1284 mode */
148 146 uchar_t current_phase; /* 1284 phase */
149 147 uchar_t backchannel; /* backchannel mode supported */
150 148 uchar_t io_mode; /* transfer mode: PIO/DMA */
151 149 /*
152 150 * Ioctls support
153 151 */
154 152 struct ecpp_transfer_parms xfer_parms; /* transfer parameters */
155 153 struct ecpp_regs regs; /* control/status registers */
156 154 uint8_t saved_dsr; /* store the dsr returned from TESTIO */
157 155 boolean_t timeout_error; /* store the timeout for GETERR */
158 156 uchar_t port; /* xfer type: dma/pio/tfifo */
159 157 struct prn_timeouts prn_timeouts; /* prnio timeouts */
160 158 /*
161 159 * ecpp.conf parameters
162 160 */
163 161 uchar_t init_seq; /* centronics init seq */
164 162 uint32_t wsrv_retry; /* delay (ms) before next wsrv */
165 163 uint32_t wait_for_busy; /* wait for BUSY to deassert */
166 164 uint32_t data_setup_time; /* pio centronics handshake */
167 165 uint32_t strobe_pulse_width; /* pio centronics handshake */
168 166 uint8_t fast_centronics; /* DMA/PIO centronics */
169 167 uint8_t fast_compat; /* DMA/PIO 1284 compatible mode */
170 168 uint32_t ecp_rev_speed; /* rev xfer speed in ECP, bytes/sec */
171 169 uint32_t rev_watchdog; /* rev xfer watchdog period, ms */
172 170 /*
173 171 * Timeouts
174 172 */
175 173 timeout_id_t timeout_id; /* io transfers timer */
176 174 timeout_id_t fifo_timer_id; /* drain SuperIO FIFO */
177 175 timeout_id_t wsrv_timer_id; /* wsrv timeout */
178 176 /*
179 177 * Softintr data
180 178 */
181 179 ddi_softintr_t softintr_id;
182 180 int softintr_flags; /* flags indicating softintr task */
183 181 uint8_t softintr_pending;
184 182 /*
185 183 * Misc stuff
186 184 */
187 185 caddr_t ioblock; /* transfer buffer block */
188 186 size_t xfercnt; /* # of bytes to transfer */
189 187 size_t resid; /* # of bytes not transferred */
190 188 caddr_t next_byte; /* next byte for PIO transfer */
191 189 caddr_t last_byte; /* last byte for PIO transfer */
192 190 uint32_t ecpp_drain_counter; /* allows fifo to drain */
193 191 uchar_t dma_cancelled; /* flushed while dma'ing */
194 192 uint8_t tfifo_intr; /* TFIFO switch interrupt workaround */
195 193 size_t nread; /* requested read */
196 194 size_t last_dmacnt; /* DMA counter value for rev watchdog */
197 195 uint32_t rev_timeout_cnt; /* number of watchdog invocations */
198 196 /*
199 197 * Spurious interrupt detection
200 198 */
201 199 hrtime_t lastspur; /* last time spurious intrs started */
202 200 long nspur; /* spurious intrs counter */
203 201 /*
204 202 * Statistics
205 203 */
206 204 kstat_t *ksp; /* kstat pointer */
207 205 kstat_t *intrstats; /* kstat interrupt counter */
208 206 /*
209 207 * number of bytes, transferred in and out in each mode
210 208 */
211 209 uint32_t ctxpio_obytes;
212 210 uint32_t obytes[ECPP_EPP_MODE+1];
213 211 uint32_t ibytes[ECPP_EPP_MODE+1];
214 212 /*
215 213 * other stats
216 214 */
217 215 uint32_t to_mode[ECPP_EPP_MODE+1]; /* # transitions to mode */
218 216 uint32_t xfer_tout; /* # transfer timeouts */
219 217 uint32_t ctx_cf; /* # periph check failures */
220 218 uint32_t joblen; /* of bytes xfer'd since open */
221 219 uint32_t isr_reattempt_high; /* max times isr has looped */
222 220 /*
223 221 * interrupt stats
224 222 */
225 223 uint_t intr_hard;
226 224 uint_t intr_spurious;
227 225 uint_t intr_soft;
228 226 /*
229 227 * identify second register set for ecp mode on Sx86
230 228 */
231 229 int noecpregs;
232 230 };
233 231
234 232 _NOTE(MUTEX_PROTECTS_DATA(ecppunit::umutex, ecppunit))
235 233 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::dip))
236 234 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::instance))
237 235 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::i_reg))
238 236 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::f_reg))
239 237 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::i_handle))
240 238 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::f_handle))
241 239 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::ecpp_trap_cookie))
242 240 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::readq))
243 241 _NOTE(DATA_READABLE_WITHOUT_LOCK(ecppunit::writeq))
244 242
245 243 /*
246 244 * current_phase values
247 245 */
248 246 #define ECPP_PHASE_INIT 0x00 /* initialization */
249 247 #define ECPP_PHASE_NEGO 0x01 /* negotiation */
250 248 #define ECPP_PHASE_TERM 0x02 /* termination */
251 249 #define ECPP_PHASE_PO 0x03 /* power-on */
252 250
253 251 #define ECPP_PHASE_C_FWD_DMA 0x10 /* cntrx/compat fwd dma xfer */
254 252 #define ECPP_PHASE_C_FWD_PIO 0x11 /* cntrx/compat fwd PIO xfer */
255 253 #define ECPP_PHASE_C_IDLE 0x12 /* cntrx/compat idle */
256 254
257 255 #define ECPP_PHASE_NIBT_REVDATA 0x20 /* nibble/byte reverse data */
258 256 #define ECPP_PHASE_NIBT_AVAIL 0x21 /* nibble/byte reverse data available */
259 257 #define ECPP_PHASE_NIBT_NAVAIL 0x22 /* nibble/byte reverse data not avail */
260 258 #define ECPP_PHASE_NIBT_REVIDLE 0x22 /* nibble/byte reverse idle */
261 259 #define ECPP_PHASE_NIBT_REVINTR 0x23 /* nibble/byte reverse interrupt */
262 260
263 261 #define ECPP_PHASE_ECP_SETUP 0x30 /* ecp setup */
264 262 #define ECPP_PHASE_ECP_FWD_XFER 0x31 /* ecp forward transfer */
265 263 #define ECPP_PHASE_ECP_FWD_IDLE 0x32 /* ecp forward idle */
266 264 #define ECPP_PHASE_ECP_FWD_REV 0x33 /* ecp forward to reverse */
267 265 #define ECPP_PHASE_ECP_REV_XFER 0x34 /* ecp reverse transfer */
268 266 #define ECPP_PHASE_ECP_REV_IDLE 0x35 /* ecp reverse idle */
269 267 #define ECPP_PHASE_ECP_REV_FWD 0x36 /* ecp reverse to forward */
270 268
271 269 #define ECPP_PHASE_EPP_INIT_IDLE 0x40 /* epp init phase */
272 270 #define ECPP_PHASE_EPP_IDLE 0x41 /* epp all-round phase */
273 271
274 272 #define FAILURE_PHASE 0x80
275 273 #define UNDEFINED_PHASE 0x81
276 274
277 275 /* ecpp return values */
278 276 #define SUCCESS 1
279 277 #define FAILURE 2
280 278
281 279 /* ecpp e_busy states */
282 280 #define ECPP_IDLE 1 /* No ongoing transfers */
283 281 #define ECPP_BUSY 2 /* Ongoing transfers on the cable */
284 282 #define ECPP_DATA 3 /* Not used */
285 283 #define ECPP_ERR 4 /* Bad status in Centronics mode */
286 284 #define ECPP_FLUSH 5 /* Currently flushing the q */
287 285
288 286 #define TRUE 1
289 287 #define FALSE 0
290 288
291 289 /* message type */
292 290 #define ECPP_BACKCHANNEL 0x45
293 291
294 292 /* transfer modes */
295 293 #define ECPP_DMA 0x1
296 294 #define ECPP_PIO 0x2
297 295
298 296 /* tuneable timing defaults */
299 297 #define CENTRONICS_RETRY 750 /* 750 milliseconds */
300 298 #define WAIT_FOR_BUSY 1000 /* 1000 microseconds */
301 299 #define SUSPEND_TOUT 10 /* # seconds before suspend fails */
302 300
303 301 /* Centronics hanshaking defaults */
304 302 #define DATA_SETUP_TIME 2 /* 2 uSec Data Setup Time (2x min) */
305 303 #define STROBE_PULSE_WIDTH 2 /* 2 uSec Strobe Pulse (2x min) */
306 304
307 305 /* 1284 Extensibility Request values */
308 306 #define ECPP_XREQ_NIBBLE 0x00 /* Nibble Mode Rev Channel Transfer */
309 307 #define ECPP_XREQ_BYTE 0x01 /* Byte Mode Rev Channel Transfer */
310 308 #define ECPP_XREQ_ID 0x04 /* Request Device ID */
311 309 #define ECPP_XREQ_ECP 0x10 /* Request ECP Mode */
312 310 #define ECPP_XREQ_ECPRLE 0x30 /* Request ECP Mode with RLE */
313 311 #define ECPP_XREQ_EPP 0x40 /* Request EPP Mode */
314 312 #define ECPP_XREQ_XLINK 0x80 /* Request Extensibility Link */
315 313
316 314 /* softintr flags */
317 315 #define ECPP_SOFTINTR_PIONEXT 0x1 /* write next byte in PIO mode */
318 316
319 317 /* Stream defaults */
320 318 #define IO_BLOCK_SZ 1024 * 128 /* transfer buffer size */
321 319 #define ECPPHIWAT 32 * 1024 * 6
322 320 #define ECPPLOWAT 32 * 1024 * 4
323 321
324 322 /* Loop timers */
325 323 #define ECPP_REG_WRITE_MAX_LOOP 100 /* cpu is faster than superio */
326 324 #define ECPP_ISR_MAX_DELAY 30 /* DMAC slow PENDING status */
327 325
328 326 /* misc constants */
329 327 #define ECPP_FIFO_SZ 16 /* FIFO size */
330 328 #define FIFO_DRAIN_PERIOD 250000 /* max FIFO drain period in usec */
331 329 #define NIBBLE_REV_BLKSZ 1024 /* send up to # bytes at a time */
332 330 #define FWD_TIMEOUT_DEFAULT 90 /* forward xfer timeout in seconds */
333 331 #define REV_TIMEOUT_DEFAULT 0 /* reverse xfer timeout in seconds */
334 332
335 333 /* ECP mode constants */
336 334 #define ECP_REV_BLKSZ 1024 /* send up to # bytes at a time */
337 335 #define ECP_REV_BLKSZ_MAX (4 * 1024) /* maximum of # bytes */
338 336 #define ECP_REV_SPEED (1 * 1024 * 1024) /* bytes/sec */
339 337 #define ECP_REV_MINTOUT 5 /* min ECP rev xfer timeout in ms */
340 338 #define REV_WATCHDOG 100 /* poll DMA counter every # ms */
341 339
342 340 /* spurious interrupt detection */
343 341 #define SPUR_CRITICAL 100 /* number of interrupts... */
344 342 #define SPUR_PERIOD 1000000000 /* in # ns */
345 343
346 344 /*
347 345 * Copyin/copyout states
348 346 */
349 347 #define ECPP_STRUCTIN 0
350 348 #define ECPP_STRUCTOUT 1
351 349 #define ECPP_ADDRIN 2
352 350 #define ECPP_ADDROUT 3
353 351
354 352 /*
355 353 * As other ioctls require the same structure, put inner struct's into union
356 354 */
357 355 struct ecpp_copystate {
358 356 int state; /* see above */
359 357 void *uaddr; /* user address of the following structure */
360 358 union {
361 359 struct ecpp_device_id devid;
362 360 struct prn_1284_device_id prn_devid;
363 361 struct prn_interface_info prn_if;
364 362 } un;
365 363 };
366 364
367 365 /*
368 366 * The structure is dynamically created for each M_IOCTL and is bound to mblk
369 367 */
370 368 _NOTE(SCHEME_PROTECTS_DATA("unique per call", ecpp_copystate))
371 369
372 370 /* kstat structure */
373 371 struct ecppkstat {
374 372 /*
375 373 * number of bytes, transferred in and out in each mode
376 374 */
377 375 struct kstat_named ek_ctx_obytes;
378 376 struct kstat_named ek_ctxpio_obytes;
379 377 struct kstat_named ek_nib_ibytes;
380 378 struct kstat_named ek_ecp_obytes;
381 379 struct kstat_named ek_ecp_ibytes;
382 380 struct kstat_named ek_epp_obytes;
383 381 struct kstat_named ek_epp_ibytes;
384 382 struct kstat_named ek_diag_obytes;
385 383 /*
386 384 * number of transitions to particular mode
387 385 */
388 386 struct kstat_named ek_to_ctx;
389 387 struct kstat_named ek_to_nib;
390 388 struct kstat_named ek_to_ecp;
391 389 struct kstat_named ek_to_epp;
392 390 struct kstat_named ek_to_diag;
393 391 /*
394 392 * other stats
395 393 */
396 394 struct kstat_named ek_xfer_tout; /* # transfer timeouts */
397 395 struct kstat_named ek_ctx_cf; /* # periph check failures */
398 396 struct kstat_named ek_joblen; /* # bytes xfer'd since open */
399 397 struct kstat_named ek_isr_reattempt_high; /* max # times */
400 398 /* isr has looped */
401 399 struct kstat_named ek_mode; /* 1284 mode */
402 400 struct kstat_named ek_phase; /* 1284 ECP phase */
403 401 struct kstat_named ek_backchan; /* backchannel mode supported */
404 402 struct kstat_named ek_iomode; /* transfer mode: pio/dma */
405 403 struct kstat_named ek_state; /* ecpp busy flag */
406 404 };
407 405
408 406 /* Macros for superio programming */
409 407 #define PP_PUTB(x, y, z) ddi_put8(x, y, z)
410 408 #define PP_GETB(x, y) ddi_get8(x, y)
411 409
412 410 #define DSR_READ(pp) PP_GETB((pp)->i_handle, &(pp)->i_reg->dsr)
413 411 #define DCR_READ(pp) PP_GETB((pp)->i_handle, &(pp)->i_reg->dcr)
414 412 #define ECR_READ(pp) \
415 413 (pp->noecpregs) ? 0xff : PP_GETB((pp)->f_handle, &(pp)->f_reg->ecr)
416 414 #define DATAR_READ(pp) PP_GETB((pp)->i_handle, &(pp)->i_reg->ir.datar)
417 415 #define DFIFO_READ(pp) \
418 416 (pp->noecpregs) ? 0xff : PP_GETB((pp)->f_handle, &(pp)->f_reg->fr.dfifo)
419 417 #define TFIFO_READ(pp) \
420 418 (pp->noecpregs) ? 0xff : PP_GETB((pp)->f_handle, &(pp)->f_reg->fr.tfifo)
421 419
422 420 #define DCR_WRITE(pp, val) PP_PUTB((pp)->i_handle, &(pp)->i_reg->dcr, val)
423 421 #define ECR_WRITE(pp, val) \
424 422 if (!pp->noecpregs) PP_PUTB((pp)->f_handle, &(pp)->f_reg->ecr, val)
425 423 #define DATAR_WRITE(pp, val) \
426 424 PP_PUTB((pp)->i_handle, &(pp)->i_reg->ir.datar, val)
427 425 #define DFIFO_WRITE(pp, val) \
428 426 if (!pp->noecpregs) PP_PUTB((pp)->f_handle, &(pp)->f_reg->fr.dfifo, val)
429 427 #define TFIFO_WRITE(pp, val) \
430 428 if (!pp->noecpregs) PP_PUTB((pp)->f_handle, &(pp)->f_reg->fr.tfifo, val)
431 429
432 430 /*
433 431 * Macros to manipulate register bits
434 432 */
435 433 #define OR_SET_BYTE_R(handle, addr, val) \
436 434 { \
437 435 uint8_t tmpval; \
438 436 tmpval = ddi_get8(handle, (uint8_t *)addr); \
439 437 tmpval |= val; \
440 438 ddi_put8(handle, (uint8_t *)addr, tmpval); \
441 439 }
442 440
443 441 #define OR_SET_LONG_R(handle, addr, val) \
444 442 { \
445 443 uint32_t tmpval; \
446 444 tmpval = ddi_get32(handle, (uint32_t *)addr); \
447 445 tmpval |= val; \
448 446 ddi_put32(handle, (uint32_t *)addr, tmpval); \
449 447 }
450 448
451 449 #define AND_SET_BYTE_R(handle, addr, val) \
452 450 { \
453 451 uint8_t tmpval; \
454 452 tmpval = ddi_get8(handle, (uint8_t *)addr); \
455 453 tmpval &= val; \
456 454 ddi_put8(handle, (uint8_t *)addr, tmpval); \
457 455 }
458 456
459 457 #define AND_SET_LONG_R(handle, addr, val) \
460 458 { \
461 459 uint32_t tmpval; \
462 460 tmpval = ddi_get32(handle, (uint32_t *)addr); \
463 461 tmpval &= val; \
464 462 ddi_put32(handle, (uint32_t *)addr, tmpval); \
465 463 }
466 464
467 465 #define NOR_SET_LONG_R(handle, addr, val, mask) \
468 466 { \
469 467 uint32_t tmpval; \
470 468 tmpval = ddi_get32(handle, (uint32_t *)addr); \
471 469 tmpval &= ~(mask); \
472 470 tmpval |= val; \
473 471 ddi_put32(handle, (uint32_t *)addr, tmpval); \
474 472 }
475 473
476 474 /*
477 475 * Macros for Cheerio/RIO DMAC programming
478 476 */
479 477 #define SET_DMAC_CSR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
480 478 ((uint32_t *)&pp->uh.ebus.dmac->csr), \
481 479 ((uint32_t)val))
482 480 #define GET_DMAC_CSR(pp) ddi_get32(pp->uh.ebus.d_handle, \
483 481 (uint32_t *)&(pp->uh.ebus.dmac->csr))
484 482
485 483 #define SET_DMAC_ACR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
486 484 ((uint32_t *)&pp->uh.ebus.dmac->acr), \
487 485 ((uint32_t)val))
488 486
489 487 #define GET_DMAC_ACR(pp) ddi_get32(pp->uh.ebus.d_handle, \
490 488 (uint32_t *)&pp->uh.ebus.dmac->acr)
491 489
492 490 #define SET_DMAC_BCR(pp, val) ddi_put32(pp->uh.ebus.d_handle, \
493 491 ((uint32_t *)&pp->uh.ebus.dmac->bcr), \
494 492 ((uint32_t)val))
495 493
496 494 #define GET_DMAC_BCR(pp) ddi_get32(pp->uh.ebus.d_handle, \
497 495 ((uint32_t *)&pp->uh.ebus.dmac->bcr))
498 496
499 497 #define DMAC_RESET_TIMEOUT 10000 /* in usec */
500 498
501 499 /*
502 500 * Macros to distinguish between PIO and DMA Compatibility mode
503 501 */
504 502 #define COMPAT_PIO(pp) (((pp)->io_mode == ECPP_PIO) && \
505 503 ((pp)->current_mode == ECPP_CENTRONICS || \
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506 504 (pp)->current_mode == ECPP_COMPAT_MODE))
507 505
508 506 #define COMPAT_DMA(pp) (((pp)->io_mode == ECPP_DMA) && \
509 507 ((pp)->current_mode == ECPP_CENTRONICS || \
510 508 (pp)->current_mode == ECPP_COMPAT_MODE))
511 509
512 510 /*
513 511 * Other useful macros
514 512 */
515 513 #define NELEM(a) (sizeof (a) / sizeof (*(a)))
514 +#if defined(__GNUC__)
515 +#define offsetof(s, m) __builtin_offsetof(s, m)
516 +#else
516 517 #define offsetof(s, m) ((size_t)(&(((s *)0)->m)))
518 +#endif
517 519
518 520 #ifdef __cplusplus
519 521 }
520 522 #endif
521 523
522 524 #endif /* _SYS_ECPPVAR_H */
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